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Integrated emission control technology is introduced in the 32-bit automotive microcontroller MPC563xM series to help reduce carbon dioxide emissions.
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The MPC563xM series includes three 32-bit powertrain MCUs to improve the efficiency and performance of small engines with one to four cylinders. Based on Power Architecture technology, the MPC563xM devices not only enhance the powertrain's capabilities, such as on-chip emissions control, but also meet the cost constraints of engine and transmission suppliers. These devices are manufactured using 90nm technology.
The MPC563xM Powertrain MCU includes a comprehensive emission control technology that leverages the functional advantages of a digital signal processing (DSP) engine built into the Power Architecture e200 core. This integrated DSP capability enables engine designers to maximize fuel economy and performance while minimizing engine “knockingâ€, reducing CO2 emissions by 3% to 5%. The DSP function is based on single-input/multi-data (SIMD) processing and can also be used as a patented sensor diagnostic mechanism to solve diagnostic problems in delivered vehicles.
There are a total of 820 million vehicles worldwide (source: JD Power and Associates), each of which emits an average of 4 tons of carbon dioxide per year, resulting in a total emissions of 3.3 billion tons. For every 5% reduction in carbon dioxide emissions from automobiles, the annual carbon dioxide emissions in the atmosphere will be reduced by 1.65 tons. Carbon dioxide is the main greenhouse gas and therefore the culprit of the global warming greenhouse effect. In the United States alone, carbon dioxide accounts for more than 80% of all greenhouse gas emissions.
The MPC563xM product line was developed by Freescale in collaboration with STMicroelectronics. Therefore, STMicroelectronics also offers a structurally similar dual source product. This unprecedented dual source arrangement helps reduce the risk of automotive customers in the supply chain.
The MPC563xM family features the following features: Power Architecture e200z3 core with 40 MHz, 60 MHz and 80 MHz options; SIMD module for DSP and floating point operations; variable length code (VLE) for up to 30 code footprint %, which increases code density and reduces memory requirements. ECC offers 768 KB, 1 MB and 1.5 MB flash options; 81 KB SRAM; 32-channel eTPU2 capable of handling complex timer applications, offloading CPU load; hardware fetching circuit – using DMA as an anti-knock filter to minimize The DSP calculates and reduces the CPU load by 5%. 2 x FlexCAN – Compatible with TouCAN and 64 + 32 buffers; 2 x eSCI; 2 x DSPI (16-bit wide), each providing up to 6 chip options, including continuous mode and DMA support. 34-channel dual-analog converter (ADC); temperature sensor at junction; 32-channel DMA controller; 196 source-interrupt controllers; Nexus IEEE-ISTO 5001-2003 Class 2+ (eTPU2 Class 1); 5V Single power supply; depending on the size of the flash memory, multiple package options are available for 100 LQFP, 144LQFP, 176 LQFP, 08 MAPBGA, and VertiCal Calibration System.
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