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Anritsu integrates channel fading simulation into the industry-leading 4G LTE-Advanced Signaling Tester MD8430A. The new digital baseband fading option turns the MD8430A signaling tester into a full-featured channel fading simulator that supports industry-standard 3GPP-defined fading curves.
The MD8430A channel fading option can be combined with the MD8430A to reduce the need to invest in additional hardware to perform signal testing under real-world radio frequency (RF) conditions. This is the first signaling solution for LTE-Advanced to support 4&TImes; 4 MIMO downlink configuration using the built-in fading simulator.
The MD8430A is trusted by development engineers for LTE and LTE-Advanced and is considered the leading signaling tester for analog lab LTE networks. With this release, the versatile MD8430A hardware platform continues to evolve, providing Anli's customers with a better return on investment.
Reflecting and scattering radio waves are transmitted through the tall structures of buildings and trees, which means that the receiver actually receives multiple original signals from "multipath" with different intensities, times and directions of arrival. A key feature of LTE-Advanced is the Multiple Input Multiple Output (MIMO) antenna system, which improves device performance by using multipath transmission. In order to test such MIMO devices more carefully and efficiently, multipath fading effects must be accurately applied to each antenna in a repeatable manner.
Using internal digital baseband processing, the MD8430A applies multipath effects during test execution, and the Rapid Test Design (RTD) software provides testers with an integrated environment for creating and running fading simulation tests. Support for LTE-Advanced features such as carrier aggregation and MIMO makes the MD8430A an ideal solution for leading chip designers to build next-generation, high-performance mobile devices. In addition to testing equipment via RF connectivity, the MD8430A with attenuation option also supports a slow clock digital interface to validate the design in a simulated environment prior to the production of expensive ASICs.
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