Application of ISD2560 Voice Chip in Queuing System

Abstract: The pin function, operation mode and specific usage method of the ISD2560 voice chip produced by Winbond are introduced in detail. The hardware structure and software design method of the voice system composed of AT89C51 and ISD2560 are given.

Keywords: single chip microcomputer; ISD2560; voice chip; ISD1425

At present, the application range of computer voice services is becoming wider and wider, such as computer voice clocks, voice-type digital multimeters, mobile phone call inquiry systems, and bus stop stations. The ISD2500 series voice chip produced by Winbond is a computer voice recording and playback device with strong functions, which can be applied to many occasions requiring voice services. The AT89C51 is a good-performance, low-cost microcontroller produced by ATMEL. This paper introduces the voice part of the intelligent queuing machine composed of AT89C51 and ISD2560, which can realize segmental recording and combined playback of voice. At the same time, it can realize whole segment or loop playback by modifying software. This paper focuses on the implementation of the function of using this circuit to complete the combined playback of voice.

The ISD2560 is a type of ISD series single-chip voice recording and playback integrated circuit. This is a permanent memory type voice recording and playback circuit with a recording time of 60s and can be recorded and replayed 100,000 times. The chip uses a patented multi-level direct analog memory technology, each sample value can be stored directly in a single EEPROM cell on-chip, so it can reproduce the voice, music, tone and effect sound very realistically and naturally, thus avoiding the general solid The quantization noise and "metal sound" caused by quantization and compression of the recording circuit. The sampling frequency of the device is 8.0kHz. The lower the sampling frequency of the same series of products, the longer the recording and playback time, but the passband and sound quality will be reduced. In addition, the ISD2560 eliminates the need for A/D and D/A converters. It is highly integrated and includes internal preamplifiers, internal clocks, timers, sample clocks, filters, automatic gain control, logic control, analog transceivers, decoders and 480 kbytes of EEPROM. The ISD2560 internal EEPROM memory cell is evenly divided into 600 rows, with 600 address cells, each of which points to one of the rows, each with an address resolution of 100 ms. In addition, the ISD2560 has the control interface required by the microcontroller. Different tasks can be accomplished by manipulating addresses and control lines to implement complex information processing functions such as combining information, connecting, setting fixed pieces of information, and managing information. The ISD2560 can be segmented or arbitrarily combined in units of minimum segment length.

1 ISD2560 pin function

The ISD2560 is available in 28-pin SOIC and 28-pin PDIP packages. Figure 1 shows its pinout. The main functions of each pin are as follows:

Power Supply (VCCA, VCCD): To minimize noise, the analog and digital circuits inside the chip use different power buses and are routed to the outer package. The analog and digital power terminals are preferably routed separately and should be connected as close as possible to the supply terminals, and the decoupling capacitors should be as close as possible to the chip.

Ground (VSSA, VSSD): Since the chip uses different analog and digital grounds, these two pins are preferably connected to ground through a low impedance path.

Power-saving control (PD): This terminal pulls high to stop the chip from entering the power-saving state. When the chip overflows, that is, the OVF terminal outputs a low level, the local end should be temporarily turned high to reset the chip; in addition, the PD terminal has a special purpose in mode 6.

Chip Select (CE): When the terminal goes low and the PD is also low, the recording and playback operations are allowed. The chip's falling edge on this end will latch the state of the address line and the P/R terminal; in addition, it has a special meaning in mode 6.

Recording mode (P/R): This terminal state is normally latched on the falling edge of CE. High level selects playback, low level selects recording. When recording, the starting address is provided by the address end until the recording continues until CE or PD goes high, or the memory overflows; if it is the former case, the chip will automatically write the EOM mark at the end of the recording. When playing, the starting address is provided by the address end, and the playback continues until the EOM mark. If the CE is always low, or the chip is operating in some mode of operation, playback will ignore the EOM and continue until an overflow occurs.

End of Message (EOM): The EOM mark is automatically inserted by the chip into the end of the segment during recording. When the playback encounters the EOM, the terminal outputs a low-level pulse. In addition, the ISD2560 chip will automatically detect the power supply voltage to maintain the integrity of the information. When the voltage is lower than 3.5V, the terminal becomes low, and the chip can only play the sound. In the mode state, it can be used to drive the LED to indicate the current working state of the chip.

figure 2

    Overflow Flag (OVF): When the chip is at the end of the memory space, the terminal outputs a low-level pulse to indicate an overflow, after which the state of the terminal follows the state of the CE terminal until the PD terminal goes high. In addition, the terminal can also be used to cascade multiple voice chips to extend the playback time.

Microphone In (MIC): This terminal is connected to the on-chip preamplifier. The on-chip automatic gain control circuit (AGC) controls the gain from -15 to 24 dB. The external microphone should be coupled to this terminal through a series capacitor. The coupling capacitor value and the 10kΩ input impedance at this end determine the low frequency cutoff point of the chip band.

Microphone Reference (MIC REF): This terminal is the reverse input of the preamplifier. When the microphone is connected in a differential form, noise can be reduced and the common mode rejection ratio can be increased.

Automatic Gain Control (AGC): The AGC dynamically adjusts the pre-gain to compensate for wide variations in the microphone input level, thus maintaining minimal distortion when recording loudly varying volumes (from whisper to click). The response time depends on the 5kΩ resistor built into the terminal and the time constant of the capacitor connected from that end to the VSSA terminal. The release time depends on the time constant set by the external parallel capacitor and resistor connected to the terminal. Satisfactory results can be obtained by selecting resistors and capacitors with nominal values ​​of 470kΩ and 4.7μF, respectively.

Analog Output (ANA OUT): Preamplifier output. Its pre-voltage gain depends on the AGC terminal level.

Analog Input (ANA IN): This terminal is the chip recording signal input. For the microphone input, the ANA OUT terminal should be connected to the terminal through an external capacitor. The capacitance and the 3kΩ input impedance of the local terminal determine the additional low-end cutoff frequency of the chip band. Other sources can be directly connected to the terminal via AC coupling.

Speaker output (SP+, SP-): It can drive speakers of 16Ω or more (the power is 12.2mW when the sound is stored inside and the power is 50mW when the AUX IN is played). For single-ended outputs, the capacitor must be indirectly coupled to the output and the speaker. The double-ended output can increase the power by a factor of four without the capacitor.

image 3

    Auxiliary input (AUX IN): When CE and P/R are high, no playback or in the playback overflow state, the input signal of this terminal will drive the speaker output through the internal amplifier. When multiple ISD2560 chips are cascaded, the speaker output of the latter stage will be connected to the output amplifier of this stage through this terminal. To prevent noise, it is recommended that when storing memory information, there should be no drive signal at this end.

External clock (XCLK): There is a pull-down component inside the terminal, which should be grounded when not in use.

Address/Mode Input (AX/MX): The role of the address side depends on the state of the highest two bits (MSB, A8 and A9). When one of the highest two bits is 0, all inputs are used as the starting address for the current recording or playback. The address end is only used as input, and the internal address information during operation is not output. The address is latched on the falling edge of CE. When the highest two bits are all 1, A0~A6 can be used for mode selection.

2 operating mode

Because the ISD2560 has several built-in modes of operation, the most features can be implemented with the fewest peripherals. The operation mode is also controlled by the address side; when the highest two bits are both 1, the other address terminals are set high to select a certain mode (or some). Therefore, the operating mode and direct addressing are mutually exclusive. The specific operation modes are listed in Table 1. The mode of operation can be implemented by a microcontroller or by hardware. There are two points to note when using the operating mode: (1) All operations are initially started from the 0 address, which is the beginning of the storage space. Subsequent operations can start from other addresses depending on the mode selected. However, the address counter will be reset to 0 after the circuit has been transferred or transcribed (except M6 mode), or both have been powered down. (2) When CE goes low and the highest two address bits are both high, the operation mode is executed. This mode of operation will remain in effect until the CE goes from high to low again, and the chip re-latches the current address/mode end level and performs the corresponding operation.

Table 1 Operating mode profile

3 Based on ISD2560 voice playback circuit design

3.1 system hardware circuit

Figure 2 shows the connection between ISD2560 and AT89C51. In the figure, the crystal oscillator Y1 of the single-chip system is 11.0593MHz, the EOM is directly connected to P1.7, and the PD is connected to P1.6. CE is connected to P3.6 and XCLK is grounded. The SN74HC573 is an address latch and the LM386N-1 is an audio power amplifier. The voice chip in this system works in the playback state, and its on-chip information can be copied by the dedicated ISD1425 advanced voice programming copy machine, so the playback quality is very good, and it can also read the storage address of each voice through it. . Figure 3 shows the playback timing diagram of the ISD2560.

3.2 System Software Design

The flow chart of the voice system software design based on ISD2560 is shown in Figure 4. Assuming that there are 20 segments of the voice segment to be played, then when a number is sent to the address corresponding to the DPTR, the EOM pin level of the voice chip must be lowered first, and then the EOM pin level is increased. Continue to read the contents of other paragraphs; otherwise, a "beep" sound will appear. In addition, you can also add some appropriate delays after each segment of speech.

4 Conclusion

The practical application of the ISD2560 voice chip in the voice recording and playback system is very good, and the programming is relatively simple. Compared with other digital voice chips, the prominent feature of the ISD2560 is that the playback effect is excellent, and the voice can be reproduced very realistically and naturally. Music, tone and effect sound, in addition, the chip can also be used to design the circuit to achieve the recording operation, which is very convenient to use.