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Don't think that the program of "changing bugs forever" is the science and technology man who loves to make mistakes. The electronic siege lion is no exception! The key is that many times, engineers don't feel that they are making mistakes. Instead, they think they have found a better solution and are happy.
In the face of a large number of components and complicated circuit diagrams, it is inevitable that engineers will make small mistakes from time to time, and maybe you will find the "New World" from which mistakes, then you will become the pioneer of the technological revolution!
But for the novice engineers who are still junior, the experience of these people may be of great benefit to you. If you have been thundered by these predecessors, you should stop stepping on it. Come and see if these 29 mistakes have you committed. Over?
Misunderstanding 1. Cost savings
Common error 1: What color is the indicator on the panel? I personally like blue, just choose it.
Positive solution: For the indicator lights on the market, the colors such as red, green, yellow and orange, regardless of the size (below 5MM) and packaging, have matured for decades, so the price is generally less than 5 cents. The blue indicator light was invented in the past three or four years. The technical maturity and supply stability are poor, so the price is four or five times more expensive. If you design a panel stack indicator color without special requirements, do not choose blue. At present, the blue indicator light is generally only used when it cannot be replaced by other colors, such as displaying a video signal.
Common error 2: These pull-down / pull-up resistors, how much resistance does not seem to have much to do with, choose an integer 5K.
Positive solution: In fact, there is no 5K resistance value in the market, the closest is 4.99K (accuracy 1%), followed by 5.1K (accuracy 5%), and its cost price is 4 times higher than the accuracy of 20% 4.7K and 2 times. The resistance of 20% precision is only 1, 1.5, 2.2, 3.3, 4.7, 6.8 (including integer multiples of 10); correspondingly, the capacitance of 20% precision is also the same as above. For resistors and capacitors, if you choose other values ​​than these, you must use higher precision, and the cost will be several times. If the accuracy is not large, it is cost. waste. In addition, the quality of the resistor is also very important. Sometimes a group of inferior resistors is enough to destroy a project. It is recommended that you buy it in a genuine self-operated mall such as Lichuang Mall.
Common mistake 3: This logic can also be used with the 74XX gate circuit, but it is too earthy, still use CPLD, it looks more upscale.
Positive solution: 74XX's door circuit is only a few cents, and CPLD has at least tens of pieces (GAL/PAL is only a few dollars, but it is not recommended), the cost has been increased many times, and it is still given to production, documentation, etc. Add several times the work. It is obviously more appropriate to use the 74XX with higher cost performance without affecting performance.
Common error 4: The PCB design requirements of this board are not high, just use a thin line and automatically cloth it.
Positive solution: automatic wiring must occupy a larger PCB area, and at the same time produce more than many times more than the manual wiring. In the large batch of products, PCB manufacturers in terms of pricing, line width, the number of vias is an important consideration. They affect the PCB yield and the consumption of the drill bit, respectively. In addition, the area of ​​the PCB is also an aspect that affects the price. Therefore, automatic wiring is bound to increase the production cost of the circuit board.
Common error 5: Our system requirements are so high, including MEM, CPU, FPGA and other chips must be the fastest.
Positive solution: In a high-speed system, not every part works at high speed, and every time the device speed is increased by one level, the price is almost doubled, and it also has a great negative impact on signal integrity issues. Therefore, when selecting a chip, it should be considered according to the degree of use of different parts of the device, rather than the fastest.
Common error 6: As long as the program is stable, the code is longer and the efficiency is not critical.
Positive solution: CPU speed and memory space are all bought with money. If you spend a few days to improve the efficiency of the program when writing code, then the cost saved by reducing the CPU frequency and reducing the memory capacity is absolutely cost-effective. The CPLD/FPGA design is similar.
Misunderstanding 2: Reliability Design
Common error 7: This board has been produced in small batches. After a long test, I found no problems. I don't need to look at the chip manual.
Positive solution: hardware design and chip application must comply with relevant specifications, especially all the parameters mentioned in the chip manual (withstand voltage, I/O level range, current, timing, temperature PCB layout, power quality, etc.) must strictly follow the settings Can not be verified by experiment. Many companies have had many painful lessons. The products have been sold for a year or two. IC manufacturers have changed their production lines, and the board will not turn. The reason is that some people’s chip parameters have changed, but they have not exceeded the manual. range. If you take the manual as the standard, then he is not afraid of how to change, if the parameters become beyond the scope of the manual, you can also find him to claim (if your board can still turn, then your reliability is even more cattle).
Common error 8: You can't blame me for a user operation error.
Positive solution: It is right to ask the user to operate strictly according to the manual. However, when the user is a human being, there is a mistake. If you can't say that you miss a wrong button, you will crash and insert a wrong plug to burn the board. Therefore, various errors that users may make must be predicted and protected in advance.
Common error 9: The reason for this board's bad is that the board on the opposite side has a problem, and it is not my responsibility.
Positive solution: There should be sufficient compatibility for various external hardware interfaces. You cannot completely strike because the other party's signal is not normal. It should not only affect the part of the function that is related to it, but other functions should work properly, should not be completely striked, or even permanently damaged, and once the interface is restored, you should immediately return to normal.
Common Mistake 10: This part of the circuit is designed to be free of problems as long as it requires software.
Positive solution: Many device features on the hardware are directly controlled by software, but the software is often buggy. After the program runs away, it is impossible to predict what will happen. The designer should ensure that no permanent damage is caused in a short period of time, regardless of the hardware in which the software is being operated.
Misunderstanding 3: System efficiency
Common error 11: Is so many tasks using interrupts or queries? Still interrupt faster.
Positive solution: The real-time nature of the interruption is strong, but not necessarily fast. If there are a lot of interrupted tasks, this does not quit, and then comes later, and the system will crash in a while. If the number of tasks is large but frequent, the CPU's great energy is used in the overhead of interrupts. The system efficiency is extremely low. If the query method is used instead, the efficiency can be greatly improved, but the query sometimes cannot meet the real-time requirements. The best way is to query in the interrupt, that is, after an interrupt, all the accumulated tasks are processed and then exited.
Common error 12: This CPU with a frequency of 100M can only handle 70%, and it is fine to change the 200M frequency.
Positive solution: The processing power of the system involves a variety of factors. In the communication service, the bottleneck is generally in the memory, the CPU is fast, and the external access is not fast.
Common error 13: CPU with a larger CACHE, it should be faster.
Positive solution: The increase of CACHE does not necessarily lead to an increase in system performance. In some cases, closing CACHE is faster than using CACHE. The reason is that the data moved to CACHE must be reused multiple times to improve system efficiency. Therefore, in the communication system, only the instruction CACHE is generally opened, and even if the data CACHE is opened, it is limited to a part of the storage space, such as the stack portion. At the same time, the program design also needs to take into account CACHE's capacity and block size. This involves the length and jump range of the key code loop body. If a loop is just a little bigger than CACHE, and it is looping repeatedly, it will be troublesome.
Common error 14: The timing of the memory interface is the factory default configuration, no need to modify.
Positive solution: The default values ​​set by the BSP for the memory interface are set according to the most conservative parameters. In practical applications, parameters such as bus operating frequency and waiting period should be properly allocated. Sometimes the frequency is lowered to increase the efficiency. For example, if the RAM access period is 70 ns and the bus frequency is 40 M, the access time of 3 cycles is 75 ns. If the bus frequency is 50 M, it must be set to 4 Cycles, the actual access time has slowed down to 80ns.
Common error 15: This CPU has a DMA module, and it is certainly faster to use it to move data.
Positive solution: The real DMA is to start the two terminals at the same time after the hardware grabs the bus, and read it in one cycle. However, many DMAs embedded in the CPU are just analog. Before starting each DMA, you need to do a lot of preparation work (set the start address and length, etc.). In the transmission, it is often read into the chip for temporary storage, and then written out, that is, It takes two clock cycles to move data once, which is faster than software to move (no need to take instructions, no extra work such as loop jump), but if you only move a few bytes at a time, you still have to do a bunch of preparations. It also involves function calls, which are not efficient. So this kind of DMA is only applicable to big data blocks, don't use it blindly.
Common error 16: A CPU can't handle it, it uses two distributed processing, and the processing power can be doubled.
Positive solution: For moving bricks, two people should be twice as efficient as one person; for painting, one more person can only help. The use of several CPUs requires more knowledge of the business before it can be determined, that is, to minimize the cost of coordination between the two CPUs, so that 1+1 is as close as possible to 2, and not less than 1.
Myth 4: Low power design
Common error 17: These bus signals are pulled with a resistor and feel relieved.
Positive solution: There are many reasons why the signal needs to be pulled up and down, but not all of them have to be pulled. The pull-down resistor pulls a simple input signal, and the current is tens of microamps or less. However, if a signal is driven, the current will reach milliamperes. The current system is usually 32 bits of address data, and there may be After the 244/245 isolated bus and other signals are pulled up, the power consumption of several watts is consumed by these resistors (do not use the concept of 8 cents per kilowatt to treat the power consumption of these watts, the reason is Look).
Common error 18: Our system is powered by 220V, so we don't care about power consumption.
Positive solution: Low-power design is not only to save power, but also has the advantage of reducing the cost of the power module and the heat dissipation system, and reducing the interference of electromagnetic radiation and thermal noise due to the reduction of current. As the temperature of the device decreases, the lifetime of the device increases accordingly (for every 10 degrees increase in the operating temperature of the semiconductor device, the lifetime is reduced by half). Power consumption issues must be considered at all times.
Common Mistake 19: The power consumption of these small chips is very low, no need to consider.
Positive solution: It is difficult to determine the power consumption of the chip that is not too complicated internally. It is mainly determined by the current on the pin. An ABT16244 consumes less than 1 mA without load, but its indicator is each foot. Can drive 60 mA load (such as matching tens of ohms of resistance), that is, the maximum power consumption of up to 60 * 16 = 960mA, of course, only the power supply current is so large, the heat is falling on the load.
Common error 20: How to deal with these unused I/O ports of CPU and FPGA? Let it be empty and say it later.
Positive solution: If the unused I/O port is left floating, it may become an input signal of repeated oscillation due to a little interference from the outside, and the power consumption of the MOS device basically depends on the number of times the gate circuit is flipped. If you pull it up, each pin will also have a micro-ampere current, so the best way is to set it as an output (of course, you can't connect other driven signals outside).
Common Mistake 21: There are so many doors left in this FPGA that you can use it.
Positive solution: The power consumption of FGPA is proportional to the number of flip-flops used and the number of flips, so the power consumption of the same model FPGA at different times of different circuits may differ by a factor of 100. Minimizing the number of flip-flops at high speeds is the fundamental way to reduce FPGA power consumption.
Common error 22: The memory has so many control signals. I only need to use OE and WE signals on this board. The chip selection is grounded, so the data is much faster when reading.
Positive solution: The power consumption of most memories will be more than 100 times larger when the chip select is valid (regardless of OE and WE), so CS should be used to control the chip as much as possible, and all other requirements should be met. It is possible to shorten the width of the chip select pulse.
Common Mistake 23: Reducing power consumption is a matter for hardware personnel, and it has nothing to do with software.
Positive solution: The hardware is just a stage. The software is the software. The access of almost every chip on the bus and the flipping of each signal are almost controlled by software. If the software can reduce the number of external accesses (use more register variables, More use of internal CACHE, etc., timely response to interrupts (interrupts are often active low with pull-up resistors) and other specific measures for specific boards will greatly reduce power consumption. In order to make the board turn well, the hardware and software must be grasped by both hands!
Common error 24: How do these signals have an overshoot? As long as the match is good, it can be eliminated.
Positive solution: Except for a few specific signals (such as 100BASE-T, CML), there are overshoots. As long as they are not very large, they do not necessarily need to match, even if the match is not the best match. The output impedance of TTL is less than 50 ohms, and some even 20 ohms. If such a large matching resistor is used, the current is very large, the power consumption is unacceptable, and the signal amplitude will be too small to be used. In addition, the output impedance of the general signal at the output high level and the output low level is not the same, and the method is completely matched. Therefore, the matching of signals such as TTL, LVDS, and 422 can be accepted as long as the overshoot is acceptable.
Myth 5: Signal Integrity
Common error 25: These signals have been simulated, and certainly no problem.
Positive solution: The simulation model cannot be exactly the same as the real thing, even the physical objects processed in different batches are different, let alone the model. Besides, the actual situation is very different, and simulation is not likely to exhaust all possibilities, especially crosstalk. There has been a lesson that a board with only a certain length of packet is extremely easy to lose packets. The last reason is that the value of the length field is 0xFF. When this data appears on the bus, it interferes with the adjacent WE signal, causing the write to not enter the RAM. . Other data will also interfere with WE, but the interference is within an acceptable range, but when the 8-bit bus is simultaneously 0-edge 1, the nearby signal can't stand. The conclusion is that the simulation results are for reference only and should be left with sufficient margin.
Common error 26: To ensure a clean power supply, the de-capacitor is much better.
Positive solution: In general, the more decoupling capacitors, the better the power supply will be, but there are too many disadvantages: waste of cost, difficulty in wiring, and too much power-on current. The key to the design of the decoupling capacitor is to select the pair of capacitors and place them in the right place. The general chip manuals have a design reference for the decoupling capacitors. It is best to follow the manual.
Common error 27: Since it is a digital signal, the edge is of course as steep as possible.
Positive solution: The steeper the edge, the wider the spectrum range, and the higher the energy of the high-frequency part; the higher the frequency, the easier the signal will be radiated (for example, a microwave radio can be made into a mobile phone, and many long-wave radio stations cannot do it) The easier it is to interfere with other signals, the worse the transmission quality of the wires themselves. Therefore, low-speed chips can be used as much as possible with low-speed chips.
Common error 28: Signal matching is really troublesome. How can I match it?
Positive solution: Generally speaking, when the signal transmission time on the wire exceeds its transition time, the reflection problem of the signal is important. The reason for the signal reflection is caused by the uneven impedance of the line. The purpose of the matching is to make the impedances of the driving end, the load end and the transmission line close, but the matching is good, and the topology of the signal line on the PCB is also A big relationship, a branch on the transmission line, a via, a corner, a connector, a change in the distance between the different locations and the ground, etc. will cause the impedance to change, and these factors will make the reflected waveform extremely complicated, very Difficult to match, so high-speed signals only use point-to-point methods to minimize problems such as vias and corners.
Common error 29: 100M data bus should be considered high frequency signal, as the clock signal frequency is only 8K, the problem is not big.
Positive solution: The value of the data bus is generally sampled by a certain edge of the control signal or the clock signal. As long as there is enough setup time and hold time for this edge, there is interference outside the range. How much impact will be (of course, the overshoot should not exceed the maximum voltage that the chip can withstand), but the clock signal is not the same as the frequency (in fact, the spectrum range is very wide), its edge is the most critical, must be guaranteed Its monotonicity, and the transition time needs to be within a certain range.
I believe that many novice engineers have had similar ideas when designing circuits. If you are also recruited, forward them to more people to see! What low-level/serious mistakes have you made? Let's share it and discuss it with everyone!
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