FPGA-based 1553B communication module design - Power Circuit - Circuit Diagram

### Introduction Active power factor correction (APFC) plays a crucial role in efficient energy utilization while minimizing environmental impact. By incorporating a power conversion circuit between the bridge rectifier and the output capacitor filter, APFC ensures that the power factor approaches unity. Operating in a high-frequency switching state, the APFC circuit offers advantages such as compact size, lightweight design, and high efficiency, making it a popular focus in power electronics research. ### Comparison of APFC Working Modes The APFC circuit can operate in one of three modes based on the continuity of the inductor current: Continuous Conduction Mode (CCM), Discontinuous Conduction Mode (DCM), and Boundary Conduction Mode (BCM). Each mode has distinct characteristics, as outlined in Table 1. This paper's APFC circuit design specifically employs the BCM mode due to its unique benefits.

Mode	Advantages	Disadvantages
CCM	High efficiency	Higher EMI issues
DCM	Simpler circuit design	Lower efficiency
BCM	Optimal balance of efficiency and simplicity	Moderate complexity

### Operation of BCM PFC Circuit Figure 1 illustrates a Boost-type PFC circuit implemented using critical conduction control. The control waveform and the inductor current waveform for a single half-cycle are depicted below. In Fig. 1(a), the circuit employs a frequency modulation scheme where an error amplifier compares the feedback signal of the output voltage with a 2.5 V reference signal. The amplified output is combined with the AC input voltage detection signal in an analog multiplier, producing a half-sine wave output synchronized with the input voltage. During the power transistor's ON period, resistor R4 detects the inductor current. When the inductor current matches the analog multiplier's output, the current comparator triggers the RS control logic, turning off the power transistor and initiating the inductor's discharge. The peak envelope of the inductor current is controlled to maintain a half-sine wave synchronized with the input voltage. Once the inductor discharges, the secondary output detects the zero-crossing of the inductor current. The RS control logic then turns the power transistor back on, completing the cycle. This dual-loop feedback system achieves Boost-type PFC operation via frequency modulation, ensuring a power factor close to unity. ### Implementation of BCM PFC Circuit The BCM Boost PFC circuit employs frequency modulation control, leveraging the MC33262 integrated control chip. This design boasts minimal peripheral components, compact size, and lightweight construction, making it ideal for small-power switching power supplies. The circuit schematic, shown in Fig. 2, consists of a Boost-type main circuit and a control circuit comprising the MC33262 device, a startup circuit, an auxiliary power supply, a current detection circuit, and a voltage detection circuit. #### Circuit Working Principle The circuit adopts a dual-loop feedback strategy. The inner loop ensures that the half-wave voltage of the full-wave rectified output, passed through resistors R2 and R4, aligns with the input voltage as a sinusoidal trajectory. The outer loop regulates the output DC voltage of the APFC converter, sampling the DC output voltage through resistors R5 and R7 before feeding it into the MC33262’s first pin. The MC33262 generates a PWM drive signal to adjust the power transistor VQ1's duty cycle, stabilizing the output voltage. As the AC input voltage varies sinusoidally from 0 V to its peak, the multiplier output adjusts the current sense comparator’s threshold, ensuring the peak current through VQ1 tracks the AC input voltage’s fluctuations. #### Circuit Design Specifications Based on the circuit principle shown in Fig. 2, the design specifications are as follows: maximum output power Pn = 150 W, input voltage range 90–270 V, output voltage Uo = 400 V, input grid frequency fac = 50 Hz, converter efficiency η ≥ 90%, minimum switching frequency fmin = 25 kHz, maximum output ripple UOP-P ≤ 8 V, and output overvoltage protection point Uovp = 440 V. #### Switching Frequency Design The switching frequency in a half-cycle is expressed as: The switching frequency f(t) dynamically adjusts within the power frequency cycle based on the input voltage. Lower power levels correspond to higher frequencies. Although theoretical limits allow frequencies up to several megahertz under light loads, higher frequencies incur greater switching losses. Control devices like the MC33262 impose upper limits; here, the maximum frequency is approximately 400 kHz. #### Inductor Design To ensure BCM operation across the entire input range, the inductor must meet specific criteria. The main inductance expression is derived as: At minimum switching frequency (fmin = 25 kHz), the largest inductance occurs when the output power is minimal and the input voltage is maximum. Using fmin = 25 kHz and Uin = 270 V, the calculated value is L = 398 μH. This design selects L = 420 μH. #### Output Diode Selection BCM addresses the reverse recovery issue of diode VD. To minimize switching tube losses, a fast recovery diode is recommended. Given the switching frequency exceeds 20 kHz, the reverse recovery time of fast and ultra-fast recovery diodes is reduced to nanoseconds, minimizing device losses and enhancing efficiency. The design specifies IDmax = 7.9 A with a safety margin. The diode’s voltage stress must exceed the output overvoltage protection point (440 V). Thus, the selected diode model is FR10J with parameters 10 A, 600 V. #### Filter Capacitor Design In the PFC circuit, a small capacitor is typically placed at the rectifier bridge output to filter high-frequency switching inductor ripple noise. Too small a capacitor may fail to suppress input noise, while too large a capacitor could cause excessive input voltage offsets. The maximum ripple voltage is expressed as ΔUCin(max). Generally, this should be less than 5% of the lowest input voltage’s peak value. The minimum input filter capacitor value is: With a minimum input voltage of 90 V, substituting the design values into equation (3) yields Cin = 2.59 μF. However, excessive capacitance distorts the reference voltage waveform, affecting the input current waveform and reducing the power factor while increasing harmonics. Therefore, the design selects Cin = 5.6 μF with a withstand voltage of 630 V, considering a margin beyond the input voltage’s peak value. This comprehensive approach ensures optimal performance while maintaining practical constraints.

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