Full range of MOS power ICs
Current probe with voltage pin, 420*4450 head diameter, 5.0mm, overcurrent current and voltage pin
L0504-Murata common mode inductor, 90Ω, 150mA
### 1. Introduction
Active Power Factor Correction (APFC) represents a crucial approach to achieving efficient energy utilization while minimizing environmental impact. By incorporating a power conversion circuit between the bridge rectifier and the output capacitor filter, APFC ensures that the power factor approaches unity. Operating in a high-frequency switching state, the active power factor correction circuit offers advantages such as compact size, lightweight design, and high efficiency. As a result, it has emerged as a focal point in the field of power electronics research.
### 2. Comparison of APFC Working Modes
The Active Power Factor Correction (APFC) circuit operates based on the continuity of the inductor current, which divides its working modes into Continuous Conduction Mode (CCM), Discontinuous Conduction Mode (DCM), and Boundary Conduction Mode (BCM). These modes exhibit distinct characteristics, as summarized in Table 1. For this paper's APFC circuit design, we adopted the BCM working mode.
### 3. Operation of BCM Power Factor Correction (PFC) Circuit
Figure 1 illustrates a schematic diagram of a Boost-type PFC circuit operating in a critical conduction control mode, along with the corresponding control waveform and power switch inductor current waveform within a half-frequency cycle. In Fig. 1(a), the circuit employs a frequency conversion control scheme where an error amplifier compares the feedback signal of the output voltage with a 2.5V reference signal and generates an amplified output. This output, combined with the AC input voltage detection signal, is fed into an analog multiplier. The multiplier produces a half-sine wave output synchronized with the input voltage. During power transistor activation, the resistor R4 detects the inductor current. Once the inductor current matches the analog multiplier’s output, the current comparison detector triggers the RS control logic to deactivate the power transistor, initiating the inductor discharge process. The peak envelope of the inductor current remains in-phase with the input voltage as a half sine wave. After discharge, the inductor’s secondary output detects the current zero-crossing. Subsequently, the RS control logic immediately reactivates the power transistor. This voltage-current dual-loop feedback control, combined with the frequency conversion control method, achieves a Boost-type PFC circuit with a power factor approaching unity.
### 4. Implementation of BCM PFC Circuit
The BCM Boost PFC circuit utilizes frequency conversion control. With minimal peripheral components, the integrated control circuit is compact and lightweight, making it ideal for small-power switching power supplies. Here, the control device MC33262 serves as the core, with the circuit schematic depicted in Fig. 2. The main circuit employs a Boost topology, while the control circuit primarily consists of the MC33262 device, a startup circuit, an auxiliary power supply, a current detection circuit, and a voltage detection circuit.
#### 4.1 Circuit Working Principle
This circuit adopts a dual-loop feedback control strategy. The inner loop feedback ensures that the half-wave voltage of the full-wave rectified output, passed through the resistor divider formed by R2 and R4, is input to pin 3 of the MC33262. This maintains the inductor-side current tracking the input voltage sinusoidally. The outer loop provides feedback control for the output DC voltage of the APFC converter. The DC output voltage is sampled via a resistor divider composed of R5 and R7 and input to pin 1 of the MC33262. The MC33262 outputs a PWM drive signal to adjust the power transistor VQ1’s duty cycle, stabilizing the output voltage. As the AC input voltage varies sinusoidally from 0V to its peak, the multiplier’s output adjusts the current sense comparator’s threshold, forcing the peak current through the power transistor VQ1 to track the input voltage’s changes.
#### 4.2 Circuit Design
Based on the circuit principle shown in Fig. 2, the technical specifications are as follows: maximum output power Pn = 150W, input voltage range 90–270V, output voltage Uo = 400V, input grid frequency fac = 50Hz, converter efficiency η = 90%, minimum switching frequency fmin = 25kHz, maximum output ripple peak-to-peak UOP-P = 8V, and output overvoltage protection point Uovp = 440V.
##### 4.2.1 Switching Frequency Design
The expression for the switching frequency in a half-frequency cycle is:
\[
f(t) = \frac{1}{2T} \left( 1 + \cos(2\pi f_{ac}t) \right)
\]
The switching frequency f(t) varies with time during the power frequency cycle for a given input voltage. Lower power corresponds to higher switching frequencies. In theory, under light load conditions, the switching frequency can reach several megahertz, but higher frequencies lead to increased switching losses. Some control devices with critical conduction modes impose limits on the maximum switching frequency. The MC33262 has a maximum frequency of approximately 400kHz.
##### 4.2.2 Inductor Design
To ensure the circuit operates in BCM across the entire operating range, the inductor must be properly designed. Thus, the main inductance expression can be derived as:
\[
L = \frac{\sqrt{2}U_{in}}{I_{Lpk}}
\]
In theory, if the minimum switching frequency is specified, the maximum inductance occurs when the output power is smallest and the input voltage is highest. A lower switching frequency minimizes switching losses, while a larger inductor reduces its size. Most designs prefer a frequency of 25kHz. Given the voltage range of 90–270V, when the input voltage Uin is 270V, substituting into formula (2) yields L = 398μH. This design uses L = 420μH.
##### 4.2.3 Output Diode Selection
BCM addresses the reverse recovery issue of diode VD. To minimize switching tube losses, a fast recovery diode is recommended. Since the switching power supply operates at frequencies above 20kHz, the reverse recovery time of fast recovery and ultra-fast recovery diodes is reduced to nanoseconds, minimizing device losses and significantly improving power efficiency. The design selects IDmax = 7.9A, with a safety margin. The diode’s voltage stress should exceed the output overvoltage protection point of 440V. Thus, the diode model is FR10J, with technical parameters of 10A and 600V.
##### 4.2.4 Filter Capacitor Design
In the PFC circuit, a small capacitor is typically connected to the rectifier bridge output to filter out high-frequency switching inductor current ripple noise. If the capacitor value is too small, high-frequency input noise may not be effectively filtered; however, if it is too large, it can cause significant input voltage offsets. The maximum ripple voltage of the filter capacitor is expressed by ΔUCin(max). Generally, the value should be less than 5% of the lowest input voltage peak. The lower limit of the input filter capacitor is:
\[
C_{in} = \frac{P_n}{2 \cdot f_{min} \cdot \Delta U_{Cin(max)}}
\]
Here, the minimum input voltage is 90V, and substituting the design index into equation (3) yields a minimum input capacitor value of Cin = 2.59μF. Since the rectifier bridge output voltage is used as the current-following reference after resistor division, excessive input capacitance distorts the reference voltage waveform, causing distortion in the input current waveform, reducing the power factor, and increasing harmonics. Therefore, the design capacitance value is 5.6μF, with a withstand voltage exceeding the maximum peak value of the input voltage and a safety margin. Hence, the circuit design selects Cin = 5.6μF and 630V.
### Conclusion
In summary, this paper presents a detailed design of a BCM-based APFC circuit. By leveraging frequency conversion control, the circuit achieves high efficiency, small size, and light weight, making it highly suitable for modern power electronic applications. Future work could explore further optimizations to enhance performance under varying load conditions.
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