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Exercise 9. Using the nesting of the state machine to achieve hierarchical structure design purposes: 1. Using the main state machine and the substate machine to generate a hierarchical logic design;
2. Flexibly use the task structure in structured design.
In the previous section, we learned how to use an instance of a state machine. In fact, the operation of a single finite state machine to control the entire logic circuit is rare in actual design. It is often the state machine that uses the state machine to form a tree-like control core. This is also consistent with the hierarchical, structured top-down design approach we advocate. Below we will provide an example for everyone to learn.
This example is a simplified serial writer for EPROM. In fact, it is a part of the EPROM reader design to achieve the write function of the abridged, remove the EPROM start, end and EPROM control word write and other functions, only have such a prototype. The steps of the work are: 1. serial write of the address; 2. serial write of the data; 3. response to the signal source, the signal source gives the next operation object; 4. end the write operation. Parallel data is output by one bit by shifting.
Module source code:
Module wriTIng(reset,clk,address,data,sda,ack);
Input reset,clk;
Input[7:0] data,address;
Output sda, ack; //sda is responsible for serial data output;
//ack is the response signal given by the module after an object has been manipulated.
Reg link_write; //link_write determines when to output.
Reg[3:0] state; //The status word of the main state machine.
Reg[4:0] sh8out_state; //From the status word of the state machine.
Reg[7:0] sh8out_buf; //Enter the data buffer.
Reg finish_F; / / used to determine whether to process an operation object.
Reg ack;
Parameter
Idle=0, addr_write=1, data_write=2, stop_ack=3;
Parameter
Bit0=1, bit1=2, bit2=3, bit3=4, bit4=5, bit5=6, bit6=7, bit7=8;
Assign sda = link_write? sh8out_buf[7] : 1'bz;
Always @(posedge clk)
Begin
If(!reset) //Reset.
Begin
Link_write<= 0;
State <= idle;
finish_F <= 0;
Sh8out_state<=idle;
Ack<= 0;
Sh8out_buf<=0;
End
Else
Case(state)
Idle:
Begin
Link_write <= 0;
State <= idle;
finish_F <= 0;
Sh8out_state<=idle;
Ack<= 0;
Sh8out_buf<=address;
State <= addr_write;
End
Addr_write: // The input of the address.
Begin
If(finish_F==0)
Begin shift8_out; end
Else
Begin
Sh8out_state <= idle;
Sh8out_buf <= data;
State <= data_write;
finish_F <= 0;
End
End
Data_write: //Write of data.
Begin
If(finish_F==0)
Begin shift8_out; end
Else
Begin
Link_write <= 0;
State <= stop_ack;
finish_F <= 0;
Ack <= 1;
End
End
Stop_ack: //Complete the response.
Begin
Ack <= 0;
State <= idle;
End
Endcase
End
Task shift8_out; // Serial write.
Begin
Case(sh8out_state)
Idle:
Begin
Link_write <= 1;
Sh8out_state <= bit0;
End
Bit0:
Begin
Link_write <= 1;
Sh8out_state <= bit1;
Sh8out_buf <= sh8out_buf<<1;
End
Bit1:
Begin
Sh8out_state<=bit2;
Sh8out_buf<=sh8out_buf<<1;
End
Bit2:
Begin
Sh8out_state<=bit3;
Sh8out_buf<=sh8out_buf<<1;
End
Bit3:
Begin
Sh8out_state<=bit4;
Sh8out_buf<=sh8out_buf<<1;
End
Bit4:
Begin
Sh8out_state<=bit5;
Sh8out_buf<=sh8out_buf<<1;
End
Bit5:
Begin
Sh8out_state<=bit6;
Sh8out_buf<=sh8out_buf<<1;
End
Bit6:
Begin
Sh8out_state<=bit7;
Sh8out_buf<=sh8out_buf<<1;
End
Bit7:
Begin
Link_write<= 0;
finish_F<=finish_F+1;
End
Endcase
End
Endtask
Endmodule
Test module source code:
`TImescale 1ns/100ps
`define clk_cycle 50
Module wriTIngTop;
Reg reset,clk;
Reg[7:0] data,address;
Wire ack, sda;
Always #`clk_cycle clk = ~clk;
iniTIal
Begin
Clk=0;
Reset=1;
Data=0;
Address=0;
#(2*`clk_cycle) reset=0;
#(2*`clk_cycle) reset=1;
#(100*`clk_cycle) $stop;
End
Always @(posedge ack) //After receiving the response signal, the next processing object is given.
Begin
Data=data+1;
Address=address+1;
End
Writing writing(.reset(reset),.clk(clk),.data(data),
.address(address),.ack(ack),.sda(sda));
Endmodule
Simulation waveform: [[wysiwyg_imageupload:252:height=174,width=496]]
Exercise: Following the above example, write a module that implements serial reading of data in the EPROM. Write a test module and give the simulation waveform.
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