j RF circuit based LDO power system design (suppression ratio and noise selection)

introduction

Portable product power supply design requires system-level thinking. When developing battery-powered devices, such as mobile phones, MP3, PDA, PMP, DSC and other low-power products, if the power system design is not reasonable, it will affect the architecture and products of the entire system. Combination of features, component selection, software design and power distribution. Similarly, in the system design, we must also consider from the perspective of saving battery energy. A low dropout linear regulator (LDO) with enable control is a good choice.

Power requirements for RF circuits

Most cellular phone baseband chipset RF circuits require three sets of power supplies: to meet the needs of digital circuits, analog circuits, and peripheral interface circuits. The baseband processor's digital circuit supply voltage is typically 1.8V to 2.6V. In general, the phone will be turned off when the Li-ion battery voltage drops to 3.2V-3.3V, and the LDO has a voltage difference of at least 500 to 600mV. The pressure difference is not high. In addition, the digital circuit itself does not require high output noise and PSRR (power supply rejection ratio) of the LDO, and requires only a very low quiescent current under light load conditions.

The baseband processor internal analog circuit supply voltage is typically 2.4V to 3.0V with a dropout voltage of 200mV to 600mV. LDOs are required to have high low frequency (217 Hz GSM phone) ripple rejection, eliminating battery voltage ripple generated by RF power amplifiers, as well as lower quiescent current specifications.

The RF supply's receive and transmit voltages are typically 2.6V to 3.0V, with low noise amplifiers (LNAs), mixers, phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), and intermediate frequencies (IF). The circuit requires a low noise, high PSRR LDO. In practical applications, the performance of VCO and PLL circuits directly affects RF circuit specifications, such as the purity of the transmitted spectrum, the selectivity of the receiver, the noise of the analog transceiver, and the phase error of the digital circuit. The noise changes the phase and amplitude characteristics of the oscillator, and the oscillator loop further amplifies the noise, possibly modulating the carrier.

LDO noise and power supply rejection ratio

LDO is a micropower low dropout linear regulator with very low self-noise and high power supply rejection ratio. The block diagram of the linear regulator is shown in Figure 1.

Figure 1 linear regulator block diagram

The PSRR is an AC parameter that reflects the input ripple rejection capability of the LDO output under the same conditions of the output and input frequencies. It is different from noise, which usually refers to interference in the frequency range of 10 Hz to 100 kHz. The expression for PSRR(dB) is as follows:

PSRR=20log(â–³Vin/â–³Vout)(1)

Figure 2 Linear regulator input and output changes

Figure 2 shows the output and input voltage curves of SGM2007 at CBP="0".01mF, ILOAD="50mA", COUT=1mF, and f=10KHz.

From equation (1), PSRR=20log(ΔVin/△Vout)=60(dB) is obtained. When the input changes by 1V, the output changes by 1mV, and the LDO ripple suppression capability is still very strong.

The output noise of the LDO is affected by its internal design and external bypass and compensation circuitry. As shown in Figure 1, the main source of LDO output noise is the reference source, and the noise generated by the reference is amplified at the output. The expression of the output noise Vn is as follows:

Vn=(R1+R2)/R2&TImes;Vref(2)

The reference source bypass capacitor CBP can affect the reference noise, and increasing the bypass capacitor can reduce the reference noise. Typical values ​​for ceramic capacitors are recommended to be 470pF to 0.01mF. The bypass capacitor affects the speed at which the LDO output voltage rises. The larger the bypass capacitor value, the slower the output voltage rise rate, so be careful when using it.

Other factors that affect LDO output noise are the internal poles, zeros, and output poles of the LDO and the magnitude of the load. Increasing the capacity of the output capacitor or mitigating the output load helps to reduce the high frequency output noise. Figure 3 shows the effect of bypass capacitor CBP on the output noise of SGM2007.

Figure 3: Effect of reference bypass capacitor on output noise value

Figure 4 shows the effect of the reference bypass capacitor on SGM2007PSRR. It can be seen that increasing the bypass capacitor increases the value of PSRR at a certain frequency.

Figure 4: Effect of reference bypass capacitor on PSRR value

The LDO requires an external input and output capacitor to be connected. Large-capacitance capacitors with lower equivalent series resistance (ESR) generally improve overall PSRR, noise, and transient response. Ceramic capacitors are usually preferred because of their low price and failure mode is open circuit, in contrast to tantalum capacitors and failure modes are short circuits and are not used. The ESR of the output capacitor affects its stability. Ceramic capacitors have a low ESR, on the order of 10 mΩ. X5R and X7R dielectric materials are recommended for ceramic capacitors because of their good temperature stability. Figure 5 and Figure 6 show the effect of output capacitor Cout on SGM2007 output noise and PSRR, respectively. It can be seen that large capacitors generally reduce output noise and increase PSRR values ​​over a range of frequencies.

Figure 6 Effect of output capacitance on PSRR value

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