IMX6 Backplane Design Guide

The MY-I.MX6 series core board requires a 5V power supply, with a continuous current of at least 2A and a peak current of 2.5A to 3A. Refer to the diagram below for details. If using a direct 5V input, the power supply must include overvoltage protection. The recommended overvoltage protection circuit is shown in the following figure. If the high voltage input is converted to 5V via DCDC, the core board will output a 3.3V power supply with a maximum current of 500mA. If the current drawn by the 3.3V on the baseboard is minimal, this 3.3V can be used as the power source for the baseboard. However, if you choose to use the 3.3V from the core board for the baseboard, ensure that a 500mA fuse is placed in series with the 3.3V line. Typically, the 3.3V on the baseboard draws more than 500mA, so most users generate their own 3.3V using DCDC or LDO. It is important to note that the 3.3V power supply on the baseboard must be enabled by the 3.3V from the core board, not directly from other sources. If there are other power supplies on the baseboard, they must also be controlled through the 3.3V from the core board. This requirement is due to the design of the I.MX6 chip. The reference circuit is shown below: For the PCB layout, it's essential to place a large capacitor near the 5V input of the core board to prevent power loss during sudden load increases. Ensure that any vias used can handle a peak current of at least 3A. Additional vias can be added to increase current capacity. Regarding the serial port design, one common issue is the reversal of RXD and TXD signals. Always refer to the schematic for proper pin definitions. For example, TXD should be connected to the CPU’s output, while RXD should be connected to the CPU’s input. When designing the baseboard, we provide both the schematic and PCB layout. The serial port uses a female connector. Make sure your design matches this configuration. If you plan to use a male connector instead, ensure that the RS232 signal connections are adjusted accordingly. More information about male and female connectors can be found online. For SD card design, follow the schematic closely for the IO pull-up and pull-down configurations. Excessive pull-up may cause the SD card to malfunction. Refer to the diagram for correct implementation. If an SD card is not needed, consider using a TF card instead, as it does not have a write-protect feature. The write-protect signal (SD3_RST/SD3_WP) should be pulled down and not left floating. If the TF card is hot-swappable, make sure you know which pin is used for detection. Typically, the detection pin is grounded when the card is inserted, and the insertion detection pin (KEY_COL/SD3_CD_B) is pulled up. If using a flip-type non-pluggable deck, the write-protect signal should be pulled up, while the insertion detection signal should be grounded (as if the card is always inserted). To improve ESD protection, ensure that the capacitance on the SD_CLK signal is small. On the PCB, the SD0, SD1, SD2, SD3, CMD, and CLK signals should be matched in length. The original ESD components should be placed close to the SD card socket. For SATA design, the principle is straightforward—ensure correct signal direction. Since the current draw of a typical SATA drive is relatively high, the 5V input should be capable of supplying at least 3A. Place the four capacitors connected in series to the SATA signal close to the SATA socket. For differential signaling, maintain a 100 ohm impedance match and control the length error between each pair to ±5 mils. A full reference ground plane is required. HDMI design must avoid incorrect pin definitions. A CM2020 protection device must not be omitted. For LVDS signals, if the transmission distance is long or the display is large, consider adding magnetic beads in series to improve signal integrity. Maintain 100 ohm differential impedance matching, control length errors to ±5 mils, and use a full reference ground plane. If using two-way LVDS for 1080p display, ensure LVDS0 and LVDS1 signals are of equal length. For RGB interface LCDs, the interface supports 24-bit and 18-bit modes. The D0–D23 signals correspond to different color bits depending on the mode. In 24-bit mode, B0–B7, G0–G7, and R0–R7 represent blue, green, and red bits respectively. In 18-bit mode, only B0–B5, G0–G5, and R0–R5 are used. Ensure the software is configured accordingly for the selected mode. If static electricity requirements are strict, add ESD protection to the LCD signals. All data lines and the CLK signal should be of equal length, and a full reference ground plane is required. For CMOS designs, the MCLK and PIXCLK signals operate at high frequencies and require isolation in layout. Data and clock signals should be matched in length, and a full reference ground plane is necessary. USB design includes support for 4 USB HOST ports and 1 10M/100M Ethernet interface via LAN9514. A coupled inductor should be placed in series on the USB line. The core board’s USB_H1_VBUS signal should be connected to 5V through a magnetic bead. If using an external power supply, include an overcurrent protection device. The MINIUSB port is only suitable for device mode; for host functionality, refer to FSL’s official OTG design. Ensure a 90 ohm differential impedance match and a full reference ground plane for USB. The external power supply must be sufficient to meet the current demand. For CAN design, the TX and RX signals operate at 3.3V, so level shifting must be considered. Ensure proper signal integrity for CANH and CANL. For PCIe design, connect a 0.1uF capacitor in series with the TX and RX signals. A 49.9 ohm resistor should be placed in parallel with the back of the capacitor on the CLK signal. Use 85 ohm differential impedance matching and a full reference ground plane.

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