IMX6 Backplane Design Guide

The MY-I.MX6 series core board requires a 5V power supply, with a continuous current of at least 2A and a peak current of 2.5A to 3A. Please refer to the diagram below for more details.

The MY-I.MX6 series core board only needs a 5V power source (a continuous current of no less than 2A, with a peak of 2.5Aâ€“3A) as an input. For more details, see the figure below.

If the power is directly supplied from a 5V source, it must be protected against overvoltage. The overvoltage protection circuit is shown below.

If the power is directly supplied from a 5V source, the 5V power source must have overvoltage protection. A protection circuit can be designed as shown in the reference.

If a high-voltage input is converted to 5V via DCDC, the core board will output a 3.3V power supply, with a maximum current of 500mA. If the current on the baseboardâ€™s 3.3V line is very low, this 3.3V can be used to power the baseboard. However, if you use the 3.3V from the core board to power the baseboard, a 500mA fuse should be placed in series on the 3.3V power line.

If high voltage is converted to 5V using a DCDC converter, the core board will output a 3.3V power supply with a maximum current of 500mA. This can be used to power the baseboard if the current on the baseboardâ€™s 3.3V line is small. In that case, a 500mA fuse should be added in series with the 3.3V power line.

Since the 3.3V on the baseboard typically draws more than 500mA, most users generate their own 3.3V using DCDC or LDO.

Since the current drawn by the 3.3V on the baseboard is usually over 500mA, most users generate another 3.3V using DCDC or LDO.

Note: The 3.3V power supply on the baseboard must be enabled by the 3.3V from the core board, not by any other power sources on the baseboard. If there are other power supplies on the baseboard, they must also be controlled by the 3.3V from the core board. This is due to the I.MX6 chipâ€™s design.

Note: The 3.3V on the baseboard must be enabled by the 3.3V from the core board, not by any other power sources on the baseboard. If there are other power sources on the baseboard, their enable signals must also be controlled by the 3.3V from the core board. This is required by the nature of the I.MX6 chip.

The reference circuit is as follows:

Reference circuit as below:

PCB

A large capacitor should be placed at the 5V input of the core board to ensure stable power delivery when the CPU load increases suddenly. If there are vias, make sure they can handle at least 3A of peak current, and consider adding more vias to increase current capacity.

A large-capacity capacitor should be placed near the 5V input on the core board to ensure continuous power supply even when the CPU experiences sudden increased load. If there are vias, ensure that they can carry at least 3A of peak current, and consider adding more vias to increase current capability.

Serial Port Design

A common issue in serial port design is the reversal of RXD and TXD signals. The reference marking in the schematic is shown below.

In serial port design, a common issue is the inversion of RXD and TXD. The standard marking in the schematic is shown below.

TXD - CPU Output

RXD - CPU Input

PCB

Note: When designing the baseboard, we provide both the schematic and PCB layout for the baseboard. The serial port uses a female connector. Ensure that the user also uses a female connector in their design. If a male connector is used, the RS232 signal connections must be adjusted accordingly. For more information about male and female connectors, please consult online resources.

Note: We can provide the schematic and PCB layout for the baseboard design. Our serial port uses a female connector. Please ensure your design matches ours. If you change the serial port to a male connector, the RS232 signal connections must be adjusted accordingly. For more information about male and female connectors, please check online resources.

SD Card Design Principle

When designing the SD card interface, the user should follow the schematic for IO pull-up and pull-down. Excessive pull-up may cause the SD card to malfunction. Refer to the diagram below for details.

For SD card design, users should strictly follow the schematic for IO pull-up and pull-down. Excessive pull-down may cause the SD card to fail. Refer to the diagram below.

Note: If the user does not need an SD card, it should be replaced with a TF card, since the TF card has no write protection. The write protection signal (SD3_RST/SD3_WP) must be pulled down and cannot be left floating. If the TF card is hot-swappable, ensure you know which pin is the detection pin. Normally, when the card is inserted, the detection pin is grounded, and the insertion detection pin (KEY_COL/SD3_CD_B) is pulled up. If a flip-type non-pluggable TF card is used, the write protection signal should be pulled up, while the insertion detection signal should be grounded (equivalent to always having the card inserted).

Note: If the user does not need an SD card but requires a TF card, since the TF card does not have a write-protect function, the write-protect signal (SD3_RST/SD3_WP) must be pulled down and cannot be left floating. If the TF card is hot-swappable, make sure you know which pin is the detection pin. Normally, when the card is inserted, the detection pin is grounded, and the insertion detection pin (KEY_COL/SD3_CD_B) is pulled up. If a flip-type non-pluggable TF card is used, the write protection signal should be pulled up, while the insertion detection signal should be grounded (equivalent to always having the card inserted).

If additional ESD protection is needed, ensure that the capacitance on the SD_CLK signal is small.

If additional ESD protection is required, ensure that the capacitance on the SD_CLK signal is small.

PCB

The SD0, SD1, SD2, SD3, CMD, and CLK signals should all be matched in length. The original ESD components are located close to the SD card holder.

The SD0, SD1, SD2, SD3, CMD, and CLK signals should be treated equally in length. The original ESD components should be placed close to the SD card socket.

SATA Design Principle

The SATA principle is relatively simple, ensuring the correct direction. Since the current of a typical SATA drive is relatively large, it is better to have a 5V input of at least 3A.

The SATA principle is simple, requiring only correct signal direction. Since the current of a typical SATA drive is relatively large, it is better to have a 5V input of at least 3A.

PCB

The four capacitors connected in series above the SATA signal should be placed close to the SATA socket.

The four capacitors connected in series with the SATA signal should be placed close to the SATA socket.

100 Ohm Differential Impedance Matching

100 Ohm differential impedance matching is required.

The length error between each differential pair should be controlled within Â±5 mils.

The length tolerance for each group of differential pairs should be controlled within Â±5 mils.

Request full reference ground plane.

A full reference ground plane is required.

HDMI Principle

The HDMI carrier must not be incorrectly defined.

The HDMI connector must not be incorrectly defined.

PCB

100 Ohm differential impedance matching is required.

The length error between each differential pair should be controlled within Â±5 mils.

A full reference ground plane is required.

The protection device CM2020 must not be omitted.

The protection component CM2020 must not be omitted.

LVDS Principle

If the LVDS signal transmission distance is long and the connected screen is large, magnetic beads can be added in series on the LVDS signal to improve signal quality.

PCB

100 Ohm differential impedance matching is required.

The length error between each differential pair should be controlled within Â±5 mils.

A full reference ground plane is required.

If a two-way LVDS signal is used for 1080p display, the LVDS0 and LVDS1 signals should be matched in length.

RGB Interface LCD (RGB Port LCD) Principle

The RGB interface LCD supports 24-bit and 18-bit interface modes.

The RGB port LCD should be matched with either a 24-bit or 18-bit interface mode.

CPU Signal (Note 1)

(CPU Signal (Note 1)) 24-bit (Note 2)

(24-bit (Note 2)) 18-bit (Note 3)

(18-bit (Note 3)) 18-bit (Note 4)

(18-bit (Note 4))

D0 B0 B0

D1 B1 B1

D2 B2 B0 B2

D3 B3 B1 B3

D4 B4 B2 B4

D5 B5 B3 B5

D6 B6 B4 G0

D7 B7 B5 G1

D8 G0 G2

D9 G1 G3

D10 G2 G0 G4

D11 G3 G1 G5

D12 G4 G2 R0

D13 G5 G3 R1

D14 G6 G4 R2

D15 G7 G5 R3

D16 R0 R4

D17 R1 R5

D18 R2 R0

D19 R3 R1

D20 R4 R2

D21 R5 R3

D22 R6 R4

D23 R7 R5

Note 1 (Note 1)

D0 indicates the lowest level of the CPU's LCD interface.

D23 indicates the highest level of the CPU's LCD interface.

Note 2 (Note 2)

B0 â€“ 24-bit LCD blue bit at the lowest level,

B7 â€“ 24-bit LCD blue bit at the highest level

G0 â€“ 24-bit LCD green bit at the lowest level,

G7 â€“ 24-bit LCD green bit at the highest level

R0 â€“ 24-bit LCD red bit at the lowest level,

R7 â€“ 24-bit LCD red bit at the highest level

Note 3 (Note 3)

With this connection, the LCD software still uses 24-bit mode.

B0 â€“ 18-bit LCD blue bit at the lowest level,

B5 â€“ 18-bit LCD blue bit at the highest level

G0 â€“ 18-bit LCD green bit at the lowest level,

G5 â€“ 18-bit LCD green bit at the highest level

R0 â€“ 18-bit LCD red bit at the lowest level,

R5 â€“ 18-bit LCD red bit at the highest level

Note 4 (Note 4)

With this connection, the LCD software should be set to 18-bit mode.

B0 â€“ 18-bit LCD blue bit at the lowest level,

B5 â€“ 18-bit LCD blue bit at the highest level

G0 â€“ 18-bit LCD green bit at the lowest level,

G5 â€“ 18-bit LCD green bit at the highest level

R0 â€“ 18-bit LCD red bit at the lowest level,

R5 â€“ 18-bit LCD red bit at the highest level

If the static electricity requirements are strict, the LCD signals should be protected with ESD components.

If there are strict ESD requirements, the LCD signals should be protected with ESD components.

PCB

All data lines and CLK signals should be equal in length.

All data lines and CLK signals should be matched in length.

A full reference ground plane is required.

CMOS Principle

PCB

The MCLK and PIXCLK signals have high frequency and should be isolated during layout.

Data and CLK signals should be matched in length.

A full reference ground plane is required.

USB Principle

The USBHOST expands 4 ports and uses LAN9514 to expand one 10M/100M Ethernet interface.

A coupled inductor is placed in series on the USB line.

The USB_H1_VBUS signal of the core board is connected to the 5V power supply through a magnetic bead.

When using an external host power supply, an overcurrent protection device should be used for USB.

The hardware design of the MINIUSB port can only be used as a device port. If you want to implement the HOST function, please refer to FSLâ€™s official OTG design.

The hardware design of the MINIUSB port can only be used as a device port. To implement the HOST function, please refer to FSLâ€™s official OTG design.

PCB

90 ohm differential impedance matching is required.

A full reference ground plane is required.

The current supplied externally should be sufficient.

CAN Principle

Due to the CAN TX and RX signals operating at 3.3V, attention should be paid to level shifting.

Since the CAN TX and RX signals operate at 3.3V, attention should be paid to level shifting.

PCB

Check the CANH and CANL signals.

PCIe Principle

TX and RX signals should be connected in series with a 0.1uF capacitor (if the RX signal already has a series capacitor on the external module, no additional capacitor is needed).

A 0.1uF capacitor is connected in series with the CLK signal, and a 49.9 ohm resistor is connected in parallel to the ground on the other end of the capacitor.

PCB

85 ohm differential impedance matching is required.

A full reference ground plane is required.

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